Sigma-Delta Converters.

Sigma-Delta Converters.

Saved in:
Bibliographic Details
Author / Creator: de la Rosa, José M.
Format: eBook Electronic
Language:English
Edition:2nd ed.
Imprint: Newark : John Wiley & Sons, Incorporated, 2018.
Series:IEEE Press Ser.
Subjects:
Metal oxide semiconductors, Complementary-Design and construction.
Analog-to-digital converters-Design and construction.
Electronic books.
Local Note:Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2022. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries.
Online Access:Click to View
Table of Contents:
  • Cover
  • Title Page
  • Copyright
  • Contents
  • Preface
  • Acknowledgements
  • List of Abbreviations
  • Chapter 1 Introduction to ΣΔ Modulators: Fundamentals, Basic Architecture and Performance Metrics
  • 1.1 Basics of Analog‐to‐Digital Conversion
  • 1.1.1 Sampling
  • 1.1.2 Quantization
  • 1.1.3 Quantization White Noise Model
  • 1.1.4 Noise Shaping
  • 1.2 Sigma‐Delta Modulation
  • 1.2.1 From Noise‐shaped Systems to ΣΔ Modulators
  • 1.2.2 Performance Metrics of ΣΔMs
  • 1.3 The First‐order ΣΔ Modulator
  • 1.4 Performance Enhancement and Taxonomy of ΣΔMs
  • 1.4.1 ΣΔM System‐level Design Parameters and Strategies
  • 1.4.2 Classification of ΣΔMs
  • 1.5 Putting All The Pieces Together: From ΣΔMs to ΣΔ ADCs
  • 1.5.1 Some Words about ΣΔ Decimators
  • 1.6 ΣΔ DACs
  • 1.6.1 System Design Trade‐offs and Signal Processing in ΣΔ DACs
  • 1.6.2 Implementation of Digital ΣΔMs used in DACs
  • 1.7 Summary
  • 1.7 References
  • Chapter 2 Taxonomy of ΣΔ Architectures
  • 2.1 Second‐order ΣΔ Modulators
  • 2.1.1 Alternative Representations of Second‐order ΣΔMs
  • 2.1.2 Second‐Order ΣΔM with Unity STF
  • 2.2 High‐order Single‐loop ΣΔMs
  • 2.3 Cascade ΣΔ Modulators
  • 2.3.1 SMASH ΣΔM Architectures
  • 2.4 Multi‐bit ΣΔ Modulators
  • 2.4.1 Influence of Multi‐bit DAC Errors
  • 2.4.2 Dynamic Element Matching Techniques
  • 2.4.3 Dual Quantization
  • 2.5 Band‐pass ΣΔ Modulators
  • 2.5.1 Quadrature BP‐ΣΔMs
  • 2.5.2 The z→−z2 LP-BP Transformation
  • 2.5.3 BP‐ΣΔMs with Optimized NTF
  • 2.5.4 Time‐interleaved and Polyphase BP‐ΣΔMs
  • 2.6 Continuous‐time ΣΔ Modulators: Architecture and Basic Concepts
  • 2.6.1 An Intuitive Analysis of CT‐ΣΔMs
  • 2.6.2 Some Words about Alias Rejection in CT‐ΣΔMs
  • 2.7 DT-CT Transformation of ΣΔMs
  • 2.7.1 The Impulse‐invariant Transformation
  • 2.7.2 DT-CT Transformation of a Second‐order ΣΔM
  • 2.8 Direct Synthesis of CT‐ΣΔMs
  • 2.9 Summary.
  • References
  • Chapter 3 Circuit Errors in Switched‐capacitor ΣΔ Modulators
  • 3.1 Overview of Nonidealities in Switched‐capacitor ΣΔ Modulators
  • 3.2 Finite Amplifier Gain in SC‐ΣΔMs
  • 3.3 Capacitor Mismatch in SC‐ΣΔMs
  • 3.4 Integrator Settling Error in SC‐ΣΔMs
  • 3.4.1 Behavioral Model for the Integrator Settling
  • 3.4.2 Linear Effect of Finite Amplifier Gain-Bandwidth Product
  • 3.4.3 Nonlinear Effect of Finite Amplifier Slew Rate
  • 3.4.4 Effect of Finite Switch On‐resistance
  • 3.5 Circuit Noise in SC‐ΣΔMs
  • 3.6 Clock Jitter in SC‐ΣΔMs
  • 3.7 Sources of Distortion in SC‐ΣΔMs
  • 3.7.1 Nonlinear Amplifier Gain
  • 3.7.2 Nonlinear Switch On‐Resistance
  • 3.8 Case Study: High‐level Sizing of a ΣΔM
  • 3.8.1 Ideal Modulator Performance
  • 3.8.2 Noise Leakages
  • 3.8.3 Circuit Noise
  • 3.8.4 Settling Error
  • 3.8.5 Overall High‐Level Sizing and Noise Budget
  • 3.9 Summary
  • References
  • Chapter 4 Circuit Errors and Compensation Techniques in Continuous‐time ΣΔ Modulators
  • 4.1 Overview of Nonidealities in Continuous‐time ΣΔ Modulators
  • 4.2 CT Integrators and Resonators
  • 4.3 Finite Amplifier Gain in CT‐ΣΔMs
  • 4.4 Time‐constant Error in CT‐ΣΔMs
  • 4.5 Finite Integrator Dynamics in CT‐ΣΔMs
  • 4.5.1 Effect of Finite Gain-Bandwidth Product on CT‐ΣΔMs
  • 4.5.2 Effect of Finite Slew Rate on CT‐ΣΔMs
  • 4.6 Sources of Distortion in CT‐ΣΔMs
  • 4.6.1 Nonlinearities in the Front‐end Integrator
  • 4.6.2 Intersymbol Interference in the Feedback DAC
  • 4.7 Circuit Noise in CT‐ΣΔMs
  • 4.7.1 Noise Analysis Considering NRZ Feedback DACs
  • 4.7.2 Noise Analysis Considering SC Feedback DACs
  • 4.8 Clock Jitter in CT‐ΣΔMs
  • 4.8.1 Jitter in Return‐to‐zero DACs
  • 4.8.2 Jitter in Non‐return‐to‐zero DACs
  • 4.8.3 Jitter in Switched‐capacitor DACs
  • 4.8.4 Lingering Effect of Clock Jitter Error.
  • 4.8.5 Reducing the Effect of Clock Jitter with FIR and Sine‐shaped DACs
  • 4.9 Excess Loop Delay in CT‐ΣΔMs
  • 4.9.1 Intuitive Analysis of ELD
  • 4.9.2 Analysis of ELD based on Impulse‐invariant DT‐CT Transformation
  • 4.9.3 Alternative ELD Compensation Techniques
  • 4.10 Quantizer Metastability in CT‐ΣΔMs
  • 4.11 Summary
  • References
  • Chapter 5 Behavioral Modeling and High‐level Simulation
  • 5.1 Systematic Design Methodology of ΣΔ Modulators
  • 5.1.1 System Partitioning and Abstraction Levels
  • 5.1.2 Sizing Process
  • 5.2 Simulation Approaches for the High‐level Evaluation of ΣΔMs
  • 5.2.1 Alternatives to Transistor‐level Simulation
  • 5.2.2 Event‐driven Behavioral Simulation Technique
  • 5.2.3 Programming Languages and Behavioral Modeling Platforms
  • 5.3 Implementing ΣΔM Behavioral Models
  • 5.3.1 From Circuit Analysis to Computational Algorithms
  • 5.3.2 Time‐domain versus Frequency‐domain Behavioral Models
  • 5.3.3 Implementing Time‐domain Behavioral Models in MATLAB
  • 5.3.4 Building Time‐domain Behavioral Models as SIMULINK C‐MEX S‐functions
  • 5.4 Efficient Behavioral Modeling of ΣΔM Building Blocks using C‐MEX S‐functions
  • 5.4.1 Modeling of SC Integrators using S‐functions
  • 5.4.2 Modeling of CT Integrators using S‐functions
  • 5.4.3 Behavioral Modeling of Quantizers using S‐functions
  • 5.5 SIMSIDES: A SIMULINK‐based Behavioral Simulator for ΣΔMs
  • 5.5.1 Model Libraries Included in SIMSIDES
  • 5.5.2 Structure of SIMSIDES and its User Interface
  • 5.6 Using SIMSIDES for High‐level Sizing and Verification of ΣΔMs
  • 5.6.1 SC Second‐order Single‐Bit ΣΔM
  • 5.6.2 CT Fifth‐order Cascade 3‐2 Multi‐bit ΣΔM
  • 5.7 Summary
  • References
  • Chapter 6 Automated Design and Optimization of ΣΔMs
  • 6.1 Architecture Exploration and Selection: Schreier's Toolbox
  • 6.1.1 Basic Functions of Schreier's Delta‐Sigma Toolbox.
  • 6.1.2 Synthesis of a Fourth‐order CRFF LP/BP SC‐ΣΔM with Tunable Notch
  • 6.1.3 Synthesis of a Fourth‐order BP CT‐ΣΔM with Tunable Notch
  • 6.2 Optimization‐based High‐level Synthesis of ΣΔ Modulators
  • 6.2.1 Combining Behavioral Simulation and Optimization
  • 6.2.2 Using Simulated Annealing as Optimization Engine
  • 6.2.3 Combining SIMSIDES with MATLAB Optimizers
  • 6.3 Lifting Method and Hardware Acceleration to Optimize CT‐ΣΔMs
  • 6.3.1 Hardware Emulation of CT‐ΣΔMs on an FPGA
  • 6.3.2 GPU‐accelerated Computing of CT‐ΣΔMs
  • 6.4 Using Multi‐objective Evolutionary Algorithms to Optimize ΣΔMs
  • 6.4.1 Combining MOEA with SIMSIDES
  • 6.4.2 Applying MOEA and SIMSIDES to the Synthesis of CT‐ΣΔMs
  • 6.5 Summary
  • References
  • Chapter 7 Electrical Design of ΣΔM: From Systems to Circuits
  • 7.1 Macromodeling ΣΔMs
  • 7.1.1 SC Integrator Macromodel
  • 7.1.2 CT Integrator Macromodel
  • 7.1.3 Nonlinear OTA Transconductor
  • 7.1.4 Embedded Flash ADC Macromodel
  • 7.1.5 Feedback DAC Macromodel
  • 7.2 Examples of ΣΔM Macromodels
  • 7.2.1 SC Second‐order Example
  • 7.2.2 Second‐order Active‐RC ΣΔM
  • 7.3 Including Noise in Transient Electrical Simulations of ΣΔMs
  • 7.3.1 Generating and Injecting Noise Data Sequences in HSPICE
  • 7.3.2 Analyzing the Impact of the Main Noise Sources in SC Integrators
  • 7.3.3 Generating and Injecting Flicker Noise Sources in Electrical Simulations
  • 7.3.4 Test Bench to Include Noise in the Simulation of ΣΔMs
  • 7.4 Processing ΣΔM Output Results of Electrical Simulations
  • 7.5 Summary
  • References
  • Chapter 8 Design Considerations of ΣΔM Subcircuits
  • 8.1 Design Considerations of CMOS Switches
  • 8.1.1 Trade‐Off Between Ron and the CMOS Switch Drain/Source Parasitic Capacitances
  • 8.1.2 Characterizing the Nonlinear Behavior of Ron
  • 8.1.3 Influence of Technology Downscaling on the Design of Switches.
  • 8.1.4 Evaluating Harmonic Distortion due to CMOS Switches
  • 8.2 Design Considerations of Operational Amplifiers
  • 8.2.1 Typical Amplifier Topologies
  • 8.2.2 Common‐mode Feedback Networks
  • 8.2.3 Characterization of the Amplifier in AC
  • 8.2.4 Characterization of the Amplifier in DC
  • 8.2.5 Characterization of the Amplifier Gain Nonlinearity
  • 8.3 Design Considerations of Transconductors
  • 8.3.1 Highly Linear Front‐end Transconductor
  • 8.3.2 Loop‐filter Transconductors
  • 8.3.3 Widely Programmable Transconductors
  • 8.4 Design Considerations of Comparators
  • 8.4.1 Regenerative Latch‐based Comparators
  • 8.4.2 Design Guidelines of Comparators
  • 8.4.3 Characterization of Offset and Hysteresis Based on the Input‐ramp Method
  • 8.4.4 Characterization of Offset and Hysteresis Based on the Bisectional Method
  • 8.4.5 Characterizing the Comparison Time
  • 8.5 Design Considerations of Current‐Steering DACs
  • 8.5.1 Fundamentals and Basic Concepts of CS DACs
  • 8.5.2 Practical Realization of CS DACs
  • 8.5.3 Current Cell Circuits, Error Limitations, and Design Criteria
  • 8.5.4 CS 4‐bit DAC Example
  • 8.6 Summary
  • References
  • Chapter 9 Practical Realization of ΣΔM: From Circuits to Chips
  • 9.1 Auxiliary ΣΔM Building Blocks
  • 9.1.1 Clock‐phase Generators
  • 9.1.2 Generation of Common‐mode Voltage, Reference Voltage, and Bias Currents
  • 9.1.3 Additional Digital Logic
  • 9.2 Layout Design, Floorplanning, and Practical Issues
  • 9.2.1 Layout Floorplanning
  • 9.2.2 I/O Pad Ring
  • 9.2.3 Importance of Layout Verification and Catastrophic Failure
  • 9.3 Chip Package, Test PCB, and Experimental Setup
  • 9.3.1 Bonding Diagram and Package
  • 9.3.2 Test PCB
  • 9.4 Experimental Test Set‐Up
  • 9.4.1 Planning the Type and Number of Instruments Needed
  • 9.4.2 Connecting Lab Instruments
  • 9.4.3 Measurement Set‐Up Example.
  • 9.5 ΣΔM Design Examples and Case Studies.

Similar Items