Hybrid CMOS Single-Electron-Transistor Device and Circuit Modeling.

Hybrid CMOS Single-Electron-Transistor Device and Circuit Modeling.

CMOS (complementary metal oxide semiconductor) is a widely accepted and utilized technology among electrical engineers involved with circuit design. SET (single electron transistor) technology has recently gained significant attention, because it can be combined with CMOSs to improve overall perform...

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Bibliographic Details
Author / Creator: Mahapatra, Santanu.
Other Authors / Creators:Ionescu, Adrian Mihai.
Format: eBook Electronic
Language:English
Imprint: Norwood : Artech House, 2006.
Series:Integrated Microsystems
Subjects:
Metal oxide semiconductors, Complementary.
Integrated circuits > Design and construction.
Electronic books.
Local Note:Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2022. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries.
Online Access:Click to View
Table of Contents:
  • Hybrid CMOS Single-Electron-Transistor Device and Circuit Design
  • Contents vii
  • Preface xiii
  • Acknowledgments xvii
  • 1 Introduction: CMOS Scaling and Single Electronics 1
  • 1.1 CMOS Scaling Limits 1
  • 1.2 Emerging Nanotechnologies: Life After CMOS 5
  • 1.3 Single-Electron Transistors-An Overview 7
  • 1.4 Short History 10
  • References 12
  • 2 Compact Modeling of SETs 15
  • 2.1 Computer-Aided Design Tools for SET Simulation 15
  • 2.2 Orthodox Theory of Single-Electron Tunneling 17
  • 2.3 Carrier Transport in SET 18
  • 2.4 Compact Modeling of SET 22
  • 2.5 Model Verification 32
  • 2.6 Subthreshold Slope 37
  • 2.7 Parameter Extraction 43
  • 2.8 Other SET Models 46
  • 2.9 SET and MOSFET Modeling Techniques-A Comparison 47
  • 2.10 Summary 47
  • References 49
  • 3 Single-Electron Transistor Logic 51
  • 3.1 Single-Electron Memory Versus Logic 51
  • 3.2 SET Inverter Characteristics 52
  • 3.3 Analysis of Inverter Characteristics 54
  • 3.4 Estimation of Power Dissipation 63
  • 3.5 Propagation Delay of SET Inverter 72
  • 3.6 Other Single-Electron Logic Gates 73
  • 3.7 Comparison Between SET and CMOS Logic 80
  • 3.8 Summary 80
  • References 81
  • 4 Hybridization of CMOS and SET 83
  • 4.1 Motivation for CMOS-SET Hybridization 83
  • 4.2 Challenges for CMOS-SET Hybridization 85
  • 4.3 CMOS-SET Cosimulation and Codesign 88
  • 4.4 Case Studies of Different Hybrid CMOS-SET Architectures 90
  • 4.5 SETMOS-Coulomb Blockade Oscillations in the Microampere Range 106
  • 4.6 Summary 121
  • References 126
  • 5 Few Electron Multiple Valued Logic and Memory Design 129
  • 5.1 Multiple Value Switching Algebra 129
  • 5.2 Motivation for MV Logic Design 130
  • 5.3 Challenges for MVL Circuit Design 134
  • 5.4 SETMOS Quaternary Logic 142
  • 5.5 SETMOS Quaternary SRAM
  • 5.6 Summary 165
  • References 165
  • 6 Fabrication of SETs and Compatibility with Silicon CMOS 169.
  • 6.1 Challenges of SET Fabrication 169
  • 6.2 Single Island SET Fabrication 173
  • 6.3 Fabrication of Multi-Island SETs 185
  • 6.4 Fabrication of CNTs and Molecular SETs 193
  • 6.5 Summary 197
  • References 199
  • Appendix A Gibbs Free Energy and Development of MIB Model 201
  • Appendix B Transconductance and Conductance Analysis of the SET 211
  • About the Authors 215
  • Index 217.

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