Nano-CMOS Circuit and Physical Design.

Nano-CMOS Circuit and Physical Design.

Based on the authors' expansive collection of notes taken over the years, Nano-CMOS Circuit and Physical Design bridges the gap between physical and circuit design and fabrication processing, manufacturability, and yield. This innovative book covers: process technology, including sub-wavelength...

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Bibliographic Details
Author / Creator: Wong, Ban.
Other Authors / Creators:Mittal, Anurag.
Cao, Yu.
Starr, Greg W.
Starr, Greg W.
Format: eBook Electronic
Language:English
Edition:1st ed.
Imprint: Hoboken : John Wiley & Sons, Incorporated, 2004.
Series:IEEE Press Ser.
Subjects:
Metal oxide semiconductors, Complementary > Design and construction.
Integrated circuits > Design and construction.
Electronic books.
Local Note:Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2022. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries.
Online Access:Click to View
Table of Contents:
  • Foreword
  • Preface
  • 1. Nano-Cmos Scaling Problems And Implications
  • 1.1. Design Methodology in the Nano-CMOS Era
  • 1.2. Innovations Needed to Continue Performance Scaling
  • 1.3. Overview of Sub-100-nm Scaling Challenges and Subwavelength Optical Lithography
  • 1.4. Process Control and Reliability
  • 1.5. Lithographic Issues and Mask Data Explosion
  • 1.6. New Breed of Circuit and Physical Design Engineers
  • 1.7. Modeling Challenges
  • 1.8. Need for Design Methodology Changes
  • 1.9. Summary
  • References
  • Part I. Process Technology And Subwavelength Optical Lithography: Physics, Theory Of Operation, Issues, And Solutions
  • 2. Cmos Device And Process Technology
  • 2.1. Equipment Requirements for Front-End Processing
  • 2.2. Front-End-Device Problems in CMOS Scaling
  • 2.3. Back-End-of-Line Technology
  • References
  • 3. Theory And Practicalities Of Subwavelength Optical Lithography
  • 3.1. Introduction and Simple Imaging Theory
  • 3.2. Challenges for the 100-nm Node
  • 3.3. Resolution Enhancement Techniques: Physics
  • 3.4. Physical Design Style Impact on RET and OPC Complexity
  • 3.5. The Road Ahead: Future Lithographic Technologies
  • References
  • Part II. Process Scaling Impact On Design
  • 4. Mixed-Signal Circuit Design
  • 4.1. Introduction
  • 4.2. Design Considerations
  • 4.3. Device Modeling
  • 4.4. Passive Components
  • 4.5. Design Methodology
  • 4.6. Low-Voltage Techniques
  • 4.7. Design Procedures
  • 4.8. Electrostatic Discharge Protection
  • 4.9. Noise Isolation
  • 4.10. Decoupling
  • 4.11. Power Busing
  • 4.12. Integration Problems
  • 4.13. Summary
  • References
  • 5. Electrostatic Discharge Protection Design
  • 5.1. Introduction
  • 5.2. ESD Standards and Models
  • 5.3. ESD Protection Design
  • 5.4. Low-C ESD Protection Design for High-Speed I/O
  • 5.5. ESD Protection Design for Mixed-Voltage I/O
  • 5.6. SCR Devices for ESD Protection
  • 5.7. Summary
  • References
  • 6. Input/Output Design
  • 6.1. Introduction
  • 6.2. I/O Standards
  • 6.3. Signal Transfer
  • 6.4. ESD Protection
  • 6.5. I/O Switching Noise
  • 6.6. Termination
  • 6.7. Impedance Matching
  • 6.8. Preemphasis
  • 6.9. Equalization
  • 6.10. Conclusion
  • References
  • 7. DRAM
  • 7.1. Introduction
  • 7.2. DRAM Basics
  • 7.3. Scaling the Capacitor
  • 7.4. Scaling the Array Transistor
  • 7.5. Scaling the Sense Amplifier
  • 7.6. Summary
  • References
  • 8. Signal Integrity Problems In On-Chip Interconnects
  • 8.1. Introduction
  • 8.2. Interconnect Parasitics Extraction
  • 8.3. Signal Integrity Analysis
  • 8.4. Design Solutions for Signal Integrity
  • 8.5. Summary
  • References
  • 9. Ultralow Power Circuit Design
  • 9.1. Introduction
  • 9.2. Design-Time Low-Power Techniques
  • 9.3. Run-Time Low-Power Techniques
  • 9.4. Technology Innovations for Low-Power Design
  • 9.5. Perspectives for Future Ultralow-Power Design
  • References
  • Part III. Impact Of Physical Design On Manufacturing/Yield And Performance
  • 10. Design For Manufacturability
  • 10.1. Introduction
  • 10.2. Comparison of Optimal and Suboptimal Layouts
  • 10.3. Global Route DFM
  • 10.4. Analog DFM
  • 10.5. Some Rules of Thumb
  • 10.6. Summary. References
  • 11. design For Variability
  • 11.1. Impact of Variations on Future Design
  • 11.2. Strategies to Mitigate Impact Due to Variations
  • 11.3. Corner Modeling Methodology for Nano-CMOS Processes
  • 11.4. New Features of the BSIM4 Model
  • 11.5. Summ

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