Nano-CMOS Circuit and Physical Design.
Based on the authors' expansive collection of notes taken over the years, Nano-CMOS Circuit and Physical Design bridges the gap between physical and circuit design and fabrication processing, manufacturability, and yield. This innovative book covers: process technology, including sub-wavelength...
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| Author / Creator: | |
|---|---|
| Other Authors / Creators: | Mittal, Anurag. Cao, Yu. Starr, Greg W. Starr, Greg W. |
| Format: | eBook Electronic |
| Language: | English |
| Edition: | 1st ed. |
| Imprint: | Hoboken : John Wiley & Sons, Incorporated, 2004. |
| Series: | IEEE Press Ser.
|
| Subjects: | |
| Local Note: | Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2022. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries. |
| Online Access: | Click to View |
| LEADER | 10146nam a22005653i 4500 | ||
|---|---|---|---|
| 001 | EBC227403 | ||
| 003 | MiAaPQ | ||
| 005 | 20220528134611.0 | ||
| 006 | m o d | | ||
| 007 | cr cnu|||||||| | ||
| 008 | 220528s2004 xx o ||||0 eng d | ||
| 020 | |a 9780471678861 |q (electronic bk.) | ||
| 020 | |z 9780471466109 | ||
| 035 | |a (MiAaPQ)EBC227403 | ||
| 035 | |a (Au-PeEL)EBL227403 | ||
| 035 | |a (CaPaEBR)ebr10114090 | ||
| 035 | |a (CaONFJC)MIL25476 | ||
| 035 | |a (OCoLC)228136455 | ||
| 040 | |a MiAaPQ |b eng |e rda |e pn |c MiAaPQ |d MiAaPQ | ||
| 050 | 4 | |a TK7871.99.M44N36 200 | |
| 082 | 0 | |a 621.39/732 | |
| 100 | 1 | |a Wong, Ban. | |
| 245 | 1 | 0 | |a Nano-CMOS Circuit and Physical Design. |
| 250 | |a 1st ed. | ||
| 264 | 1 | |a Hoboken : |b John Wiley & Sons, Incorporated, |c 2004. | |
| 264 | 4 | |c ©2005. | |
| 300 | |a 1 online resource (413 pages) | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 490 | 1 | |a IEEE Press Ser. | |
| 505 | 0 | |a Intro -- NANO-CMOS CIRCUIT AND PHYSICAL DESIGN -- CONTENTS -- FOREWORD -- PREFACE -- 1 NANO-CMOS SCALING PROBLEMS AND IMPLICATIONS -- 1.1 Design Methodology in the Nano-CMOS Era -- 1.2 Innovations Needed to Continue Performance Scaling -- 1.3 Overview of Sub-100-nm Scaling Challenges and Subwavelength Optical Lithography -- 1.3.1 Back-End-of-Line Challenges (Metallization) -- 1.3.2 Front-End-of-Line Challenges (Transistors) -- 1.4 Process Control and Reliability -- 1.5 Lithographic Issues and Mask Data Explosion -- 1.6 New Breed of Circuit and Physical Design Engineers -- 1.7 Modeling Challenges -- 1.8 Need for Design Methodology Changes -- 1.9 Summary -- References -- PART I PROCESS TECHNOLOGY AND SUBWAVELENGTH OPTICAL LITHOGRAPHY: PHYSICS, THEORY OF OPERATION, ISSUES, AND SOLUTIONS -- 2 CMOS DEVICE AND PROCESS TECHNOLOGY -- 2.1 Equipment Requirements for Front-End Processing -- 2.1.1 Technical Background -- 2.1.2 Gate Dielectric Scaling -- 2.1.3 Strain Engineering -- 2.1.4 Rapid Thermal Processing Technology -- 2.2 Front-End-Device Problems in CMOS Scaling -- 2.2.1 CMOS Scaling Challenges -- 2.2.2 Quantum Effects Model -- 2.2.3 Polysilicon Gate Depletion Effects -- 2.2.4 Metal Gate Electrodes -- 2.2.5 Direct-Tunneling Gate Leakage -- 2.2.6 Parasitic Capacitance -- 2.2.7 Reliability Concerns -- 2.3 Back-End-of-Line Technology -- 2.3.1 Interconnect Scaling -- 2.3.2 Copper Wire Technology -- 2.3.3 Low-κ Dielectric Challenges -- 2.3.4 Future Global Interconnect Technology -- References -- 3 THEORY AND PRACTICALITIES OF SUBWAVELENGTH OPTICAL LITHOGRAPHY -- 3.1 Introduction and Simple Imaging Theory -- 3.2 Challenges for the 100-nm Node -- 3.2.1 κ-Factor for the 100-nm Node -- 3.2.2 Significant Process Variations -- 3.2.3 Impact of Low-κ Imaging on Process Sensitivities -- 3.2.4 Low-κ Imaging and Impact on Depth of Focus. | |
| 505 | 8 | |a 3.2.5 Low-κ Imaging and Exposure Tolerance -- 3.2.6 Low-κ Imaging and Impact on Mask Error Enhancement Factor -- 3.2.7 Low-κ Imaging and Sensitivity to Aberrations -- 3.2.8 Low-κ Imaging and CD Variation as a Function of Pitch -- 3.2.9 Low-κ Imaging and Corner Rounding Radius -- 3.3 Resolution Enhancement Techniques: Physics -- 3.3.1 Specialized Illumination Patterns -- 3.3.2 Optical Proximity Corrections -- 3.3.3 Subresolution Assist Features -- 3.3.4 Alternating Phase-Shift Masks -- 3.4 Physical Design Style Impact on RET and OPC Complexity -- 3.4.1 Specialized Illumination Conditions -- 3.4.2 Two-Dimensional Layouts -- 3.4.3 Alternating Phase-Shift Masks -- 3.4.4 Mask Costs -- 3.5 The Road Ahead: Future Lithographic Technologies -- 3.5.1 The Evolutionary Path: 157-nm Lithography -- 3.5.2 Still Evolutionary: Immersion Lithography -- 3.5.3 Quantum Leap: EUV Lithography -- 3.5.4 Particle Beam Lithography -- 3.5.5 Direct-Write Electron Beam Tools -- References -- PART II PROCESS SCALING IMPACT ON DESIGN -- 4 MIXED-SIGNAL CIRCUIT DESIGN -- 4.1 Introduction -- 4.2 Design Considerations -- 4.3 Device Modeling -- 4.4 Passive Components -- 4.5 Design Methodology -- 4.5.1 Benchmark Circuits -- 4.5.2 Design Using Thin Oxide Devices -- 4.5.3 Design Using Thick Oxide Devices -- 4.6 Low-Voltage Techniques -- 4.6.1 Current Mirrors -- 4.6.2 Input Stages -- 4.6.3 Output Stages -- 4.6.4 Bandgap References -- 4.7 Design Procedures -- 4.8 Electrostatic Discharge Protection -- 4.8.1 Multiple-Supply Concerns -- 4.9 Noise Isolation -- 4.9.1 Guard Ring Structures -- 4.9.2 Isolated NMOS Devices -- 4.9.3 Epitaxial Material versus Bulk Silicon -- 4.10 Decoupling -- 4.11 Power Busing -- 4.12 Integration Problems -- 4.12.1 Corner Regions -- 4.12.2 Neighboring Circuitry -- 4.13 Summary -- References -- 5 ELECTROSTATIC DISCHARGE PROTECTION DESIGN -- 5.1 Introduction. | |
| 505 | 8 | |a 5.2 ESD Standards and Models -- 5.3 ESD Protection Design -- 5.3.1 ESD Protection Scheme -- 5.3.2 Turn-on Uniformity of ESD Protection Devices -- 5.3.3 ESD Implantation and Silicide Blocking -- 5.3.4 ESD Protection Guidelines -- 5.4 Low-C ESD Protection Design for High-Speed I/O -- 5.4.1 ESD Protection for High-Speed I/O or Analog Pins -- 5.4.2 Low-C ESD Protection Design -- 5.4.3 Input Capacitance Calculations -- 5.4.4 ESD Robustness -- 5.4.5 Turn-on Verification -- 5.5 ESD Protection Design for Mixed-Voltage I/O -- 5.5.1 Mixed-Voltage I/O Interfaces -- 5.5.2 ESD Concerns for Mixed-Voltage I/O Interfaces -- 5.5.3 ESD Protection Device for a Mixed-Voltage I/O Interface -- 5.5.4 ESD Protection Circuit Design for a Mixed-Voltage I/O Interface -- 5.5.5 ESD Robustness -- 5.5.6 Turn-on Verification -- 5.6 SCR Devices for ESD Protection -- 5.6.1 Turn-on Mechanism of SCR Devices -- 5.6.2 SCR-Based Devices for CMOS On-Chip ESD Protection -- 5.6.3 SCR Latch-up Engineering -- 5.7 Summary -- References -- 6 INPUT/OUTPUT DESIGN -- 6.1 Introduction -- 6.2 I/O Standards -- 6.3 Signal Transfer -- 6.3.1 Single-Ended Buffers -- 6.3.2 Differential Buffers -- 6.4 ESD Protection -- 6.5 I/O Switching Noise -- 6.6 Termination -- 6.7 Impedance Matching -- 6.8 Preemphasis -- 6.9 Equalization -- 6.10 Conclusion -- References -- 7 DRAM -- 7.1 Introduction -- 7.2 DRAM Basics -- 7.3 Scaling the Capacitor -- 7.4 Scaling the Array Transistor -- 7.5 Scaling the Sense Amplifier -- 7.6 Summary -- References -- 8 SIGNAL INTEGRITY PROBLEMS IN ON-CHIP INTERCONNECTS -- 8.1 Introduction -- 8.1.1 Interconnect Figures of Merit -- 8.2 Interconnect Parasitics Extraction -- 8.2.1 Circuit Representation of Interconnects -- 8.2.2 RC Extraction -- 8.2.3 Inductance Extraction -- 8.3 Signal Integrity Analysis -- 8.3.1 Interconnect Driver Models -- 8.3.2 RC Interconnect Analysis. | |
| 505 | 8 | |a 8.3.3 RLC Interconnect Analysis -- 8.3.4 Noise-Aware Timing Analysis -- 8.4 Design Solutions for Signal Integrity -- 8.4.1 Physical Design Techniques -- 8.4.2 Circuit Techniques -- 8.5 Summary -- References -- 9 ULTRALOW POWER CIRCUIT DESIGN -- 9.1 Introduction -- 9.2 Design-Time Low-Power Techniques -- 9.2.1 System- and Architecture-Level Design-Time Techniques -- 9.2.2 Circuit-Level Design-Time Techniques -- 9.2.3 Memory Techniques at Design Time -- 9.3 Run-Time Low-Power Techniques -- 9.3.1 System- and Architecture-Level Run-Time Techniques -- 9.3.2 Circuit-Level Run-Time Techniques -- 9.3.3 Memory Techniques at Run Time -- 9.4 Technology Innovations for Low-Power Design -- 9.4.1 Novel Device Technologies -- 9.4.2 Assembly Technology Innovations -- 9.5 Perspectives for Future Ultralow-Power Design -- 9.5.1 Subthreshold Circuit Operation -- 9.5.2 Fault-Tolerant Design -- 9.5.3 Asynchronous versus Synchronous Design -- 9.5.4 Gate-Induced Leakage Suppression Schemes -- References -- PART III IMPACT OF PHYSICAL DESIGN ON MANUFACTURING/YIELD AND PERFORMANCE -- 10 DESIGN FOR MANUFACTURABILITY -- 10.1 Introduction -- 10.2 Comparison of Optimal and Suboptimal Layouts -- 10.3 Global Route DFM -- 10.4 Analog DFM -- 10.5 Some Rules of Thumb -- 10.6 Summary -- References -- 11 DESIGN FOR VARIABILITY -- 11.1 Impact of Variations on Future Design -- 11.1.1 Parametric Variations in Circuit Design -- 11.1.2 Impact on Circuit Performance -- 11.2 Strategies to Mitigate Impact Due to Variations -- 11.2.1 Clock Distribution Strategies to Minimize Skew -- 11.2.2 SRAM Techniques to Deal with Variations -- 11.2.3 Analog Strategies to Deal with Variations -- 11.2.4 Digital Circuit Strategies to Deal with Variations -- 11.3 Corner Modeling Methodology for Nano-CMOS Processes -- 11.3.1 Need for Statistical Models -- 11.3.2 Statistical Model Use. | |
| 505 | 8 | |a 11.4 New Features of the BSIM4 Model -- 11.4.1 Halo/Pocket Implant -- 11.4.2 Gate-Induced Drain Leakage and Gate Direct Tunneling -- 11.4.3 Modeling Challenges -- 11.4.4 Model-Specific Issues -- 11.4.5 Model Summary -- 11.5 Summary -- References -- INDEX. | |
| 520 | |a Based on the authors' expansive collection of notes taken over the years, Nano-CMOS Circuit and Physical Design bridges the gap between physical and circuit design and fabrication processing, manufacturability, and yield. This innovative book covers: process technology, including sub-wavelength optical lithography; impact of process scaling on circuit and physical implementation and low power with leaky transistors; and DFM, yield, and the impact of physical implementation. | ||
| 588 | |a Description based on publisher supplied metadata and other sources. | ||
| 590 | |a Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2022. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries. | ||
| 650 | 0 | |a Metal oxide semiconductors, Complementary -- Design and construction. | |
| 650 | 0 | |a Integrated circuits -- Design and construction. | |
| 655 | 4 | |a Electronic books. | |
| 700 | 1 | |a Mittal, Anurag. | |
| 700 | 1 | |a Cao, Yu. | |
| 700 | 1 | |a Starr, Greg W. | |
| 700 | 1 | |a Starr, Greg W. | |
| 776 | 0 | 8 | |i Print version: |a Wong, Ban |t Nano-CMOS Circuit and Physical Design |d Hoboken : John Wiley & Sons, Incorporated,c2004 |z 9780471466109 |
| 797 | 2 | |a ProQuest (Firm) | |
| 830 | 0 | |a IEEE Press Ser. | |
| 856 | 4 | 0 | |u https://ebookcentral.proquest.com/lib/well/detail.action?docID=227403 |z Click to View |